In contrast to conventional planar metal-oxide-semiconductor field-effect transistors (“MOSFETs”), multi-gate transistors incorporate two or more gates into a single device. Relative to single gate transistors, multi-gate transistors reduce off-state current leakage, increase on-state current flow, and reduce overall power consumption. Multi-gate devices having non-planar topographies also tend to be more compact than conventional planar transistors and consequently permit higher device densities to be achieved.
One known type of non-planar, multi-gate transistor, commonly referred to as a “FinFET,” includes two or more parallel fins (“fin structures”) formed on a semiconductor substrate and extending in a longitudinal direction. FinFETs further include at least one conductive gate structure that is formed over the fin structures and generally extends in a lateral direction perpendicular to the longitudinal direction. Source and drain regions are formed in each fin structure on opposite sides of the gate structure. The gate extends across and over the fin structures such that an intermediate region of the gate conformally overlays three surfaces of each fin structure (i.e., an upper surface, a first sidewall surface, and a second opposing sidewall surface of each fin). Because the gate structure surrounds the fin structure on three surfaces, the FinFET essentially has three gates controlling the current through the fin structure or channel region. These three gates provide three channels for electrical signals to travel, thus effectively increasing the conductivity per unit surface area as compared to a conventional planar transistor.
While providing the advantages noted above, FinFETs and other non-planar multi-gate devices utilizing fin structures (e.g., TriFETs) can be somewhat difficult to fabricate due to their unique topographies, particularly at advanced technology nodes. One particular difficulty is encountered when forming contacts at the source and drain regions. Specifically, as pitch shrinks it is difficult to grow epitaxial material on source and drain regions for contact formation without merging the epitaxial material across adjacent fins. Further, even if the epitaxial material does not become merged across fins, non-uniformity in the thickness of epitaxial material on fin structures provides a detrimental impact to device performance.
Accordingly, it is desirable to provide integrated circuits with improved fin structures and methods for fabricating such integrated circuits. Also, it is desirable to provide integrated circuits with laterally confined epitaxial material overlying fin structures and methods for fabricating such integrated circuits. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.